tangxifan
tangxifan
#### Motivation of Refactoring effort A detailed technical plan can be found at [link](https://docs.google.com/document/d/15m7IbVRbQYLxFQjIVNIZT3VjYDhAqK6cjqCxVuSVDGU/edit?usp=sharing) The overall refactoring effort aims to - create a unified data structure ``RRGraphView`` as a centralized...
## Expected Behavior The behavioral/functional Verilog netlists should work in HDL simulation ## Actual Behavior The behavioral Verilog netlist of High-Density standard cell `stdfrtp` has critical bugs which causes HDL...
**Is your feature request related to a problem? Please describe.** For user-friendly pin constraint support, the tool requires a device pin map for diverse FPGA architecture/devices. As FPGA sizes are...
**Is your feature request related to a problem? Please describe.** Currently, the bus group file has to be manually written as an input for OpenFPGA. However, the bus group file...
> **Describe the bug** > A clear and concise description of what the bug is. - [x] FPGA-Verilog > **To Reproduce** > Steps to reproduce the behavior: > 1. Clone...
**Is your feature request related to a problem? Please describe.** OpenFPGA has supported the [bus group file](https://openfpga.readthedocs.io/en/master/manual/file_formats/bus_group_file/) format which can generate verilog testbenches as well as preconfigured wrapper modules with...
> **Describe the bug** > A clear and concise description of what the bug is. - [x] Documentation > **To Reproduce** > Steps to reproduce the behavior: > 1. Clone...
**Is your feature request related to a problem? Please describe.** Currently, OpenFPGA's Verilog testbench generators only support random vectors. It has significant drawbacks: - This is very limited in testing...
**Is your feature request related to a problem? Please describe.** Scan chain has been widely used in SOFA project because enables testable FPGA fabric. The scan chain organization follows a...
**Describe the bug** As OpenFPGA now supports multi-clock FPGAs, the analysis SDC writer still supports only single-clock devices. The restrictions have to be removed. **To Reproduce** Codes with assertations: https://github.com/lnis-uofu/OpenFPGA/blob/a1aade5d018a1d3d17ef71d61cc674ef61aa19db/openfpga/src/fpga_sdc/analysis_sdc_writer.cpp#L85-L88...