Support VCD files when generating testing vectors in testbenches

[tangxifan]

Is your feature request related to a problem? Please describe.

Currently, OpenFPGA's Verilog testbench generators only support random vectors. It has significant drawbacks:

• This is very limited in testing coverage. For many practical applications, e.g., BRAM and DSP, testing patterns have to be carefully selected.
• The auto-generated testbench requires significant manual effort when modifying to adapt different testing vectors

Due to the reasons above, verification through OpenFPGA' testbenches is not easy.

Describe the solution you'd like We should consider to support .vcd file in testbench generator (https://en.wikipedia.org/wiki/Value_change_dump) .vcd is commonly used as a exchangeable file format in defining signal vectors. OpenFPGA's testbench generator can parse a .vcd file and apply the testing vectors in both

• full testbench
• preconfigured testbench

We may consider to evaluate and integrate the following C++ -based VCD parser:

• https://github.com/ben-marshall/verilog-vcd-parser
• https://github.com/kmurray/libvcdparse

Describe alternatives you've considered Other than .vcd files, we can think about other file format which allow users to define testing vectors easily.