Automate bus group file generation in openfpga flow

[tangxifan]

Is your feature request related to a problem? Please describe. Currently, the bus group file has to be manually written as an input for OpenFPGA. However, the bus group file can be long and cumbersome to write, when HDL designs are huge. On the other side, the bus group file can be automatically generated using python scripts: Python libraries such as PyVerilog can parse an HDL design and get port information.

Describe the solution you'd like Therefore, I propose that bus group file can be generated on-fly when running the openfpga flow

New syntax in the task configuration file:

• The bus group file auto-generation can be enabled by a switch under general setting: bus_group_file_generation=[on|off]
• When enabled, a bus group file will be generated under the runtime directory. It will auto-fill the variable in the task configuration, e.g., bench0_openfpga_bus_group_file, for each benchmark

https://github.com/lnis-uofu/OpenFPGA/blob/70e2330f1740786ac7a108fd4182d63ab75069d3/openfpga_flow/tasks/basic_tests/bus_group/full_testbench_explicit_mapping/config/task.conf#L45

• Requires the openfpga shell script have a variable ${OPENFPGA_BUS_GROUP_FILE} define. For example:

https://github.com/lnis-uofu/OpenFPGA/blob/70e2330f1740786ac7a108fd4182d63ab75069d3/openfpga_flow/openfpga_shell_scripts/full_testbench_bus_group_example_script.openfpga#L58