Undriven nets in Flip-Flop Verilog Netlists

[tangxifan]

Expected Behavior

The behavioral/functional Verilog netlists should work in HDL simulation

Actual Behavior

The behavioral Verilog netlist of High-Density standard cell stdfrtp has critical bugs which causes HDL simulation fails. A quick example:

https://cs.opensource.google/skywater-pdk/skywater-pdk/+/master:libraries/sky130_fd_sc_hd/latest/cells/sdfrtp/sky130_fd_sc_hd__sdfrtp.behavioral.v;l=80

**Same problem may happen to other flip-flop netlists``

You can see the nets D_delayed, SCD_delayed and CLK_delayed are undriven nets which are denoted as X signals in HDL simulations. As a result, the flip-flop Verilog netlist is malfunctional.

Steps to Reproduce the Problem

1. See example netlist

Specifications

• Version: Latest master
• Platform: CentOS 7

[abdullahyildiz]

@mithro,

I had the same issue as explained above by @tangxifan.