Check valid net names in Pin Constraint File (PCF) after parsing

[tangxifan]

Describe the bug A clear and concise description of what the bug is.

• [x] FPGA-Verilog

To Reproduce Steps to reproduce the behavior:

1. Clone OpenFPGA repository and checkout commit id: 70e2330
2. Execute OpenFPGA task or your own example:

• Change the following line to net="reset_wrong"

https://github.com/lnis-uofu/OpenFPGA/blob/70e2330f1740786ac7a108fd4182d63ab75069d3/openfpga_flow/tasks/benchmark_sweep/counter8/config/pin_constraints_reset.xml#L5

• Run the openfpga flow on this task ``benchmark_sweep/counter8

3. See error when running iVerilog simulation.

Expected behavior The error should be flagged right after reading the pcf files:

https://github.com/lnis-uofu/OpenFPGA/blob/70e2330f1740786ac7a108fd4182d63ab75069d3/openfpga/src/base/openfpga_verilog.cpp#L239-L243

Enviornment (please complete the following information):

• OS:

• [x] Ubuntu 20.04

• Compiler:

• [x] gcc-8

• Version: