Jiuyang Liu

icon indicating an email [email protected]

icon location Wuhan, China icon location 0x8D7B5A. I work for open source chip design.

Results 142 issues of Jiuyang Liu

[LTL][SVA] Proposal for Explicit Clocking in the CIRCT LTL(SVA) Intermediate Representation

2 comment

# Analysis of SystemVerilog Assertions (SVA) Clocking Semantics: A Foundation for Ambiguity In SystemVerilog, concurrent assertions without an explicit clocking event infer the clock from the surrounding context. This "action...

[proposal] add reference sail implementation for each instruction

In our downstream repository: https://github.com/chipsalliance/rvdecoderdb/pull/39 We are experimenting with adding a sail code snippet for each single instruction, for example: https://github.com/rez5427/rvdecoderdb/blob/sailcodegen/rvdecoderdbtest/jvm/src/sail/inst/rv_i/addi We are wondering would it be possible for riscv-opcodes...