Jiuyang Liu
Jiuyang Liu
I didn't make it optional, ask @jerryz123 to take over;p **Related issue**: **Type of change**: bug report | feature request | other enhancement **Impact**: no functional change | API addition...
- **circt: 1.83 -> 1.84** - **circt: add sequencer to maintainers** ## Description of changes ## Things done - Built on platform(s) - [ ] x86_64-linux - [ ] aarch64-linux...
Our new PnR infrastructure(inhouse) depends on this.
Since [T1](https://github.com/chipsalliance/t1.git) implemented `LMUL=1/8` in `EEW=32` case. we submit this PR for consideration: making `e8mf8` type to be allowed when `VLEN>=64` and `EEW=32`, the common case of `VLEN` is `VLEN>>EEW`,...
Motivation = Chisel has long lacked a unified and robust approach for exposing metadata. Several prior attempts—such as RocketChip OM/OM2, the Trace API, and the current Property & Class API—have...
We are trying to link SystemVerilog against FIRRTL at CIRCT time. I'm requesting a API to expose SystemVerilog as FIRRTL Blackbox, being able to inspect via C-API, which can be...
``` error: builder for '/nix/store/cpr1ghp2cz94rp6h9i4prcg1aw109d0f-sn-bindgen-sbt-dependencies.tar.zst.drv' failed with exit code 1; last 25 log lines: > [error] at scala.Function1.$anonfun$compose$1(Function1.scala:49) > [error] at sbt.internal.util.$tilde$greater.$anonfun$$u2219$1(TypeFunctions.scala:63) > [error] at sbt.std.Transform$$anon$4.work(Transform.scala:69) > [error] at sbt.Execute.$anonfun$submit$2(Execute.scala:283)...
Problem Statement --- FIRRTL’s intermediate representation already defines a `BitCastOp` for bit-level reinterpreting between equal-width types (`Bundles`, `Vecs`, `UInt`, `SInt`, etc.), but this operator currently lacks parser/printer (ser/deser) support. As...