Jiuyang Liu
Jiuyang Liu
In order to feed Documentation to Typst template, as well as PnR scripts. T1 will use Object Model in MLIR. The OM information will be stored via Property API in...
The basic verification idea of T1 IP is based on the online difftest. However when we are getting bigger and bigger, verification becomes a new problem, which we need to...
The current uArch of T1 is not a **micro** arch now, appending to a lot of parameters, it is going to be another giant In order to deliver this to...
Originally in RocketChip, we use SBT to generate jar and execute it to generate Verilog, which was a nightmare to maintain, thus we eventually switch to mill for managing this...
Since Chisel has supported LTL via intmodule, I think it might be a good idea to upstream LTL as a part of firrtl spec. This cleans up the fir file...
This PR removes `message` field in cover, according to [reply](https://github.com/chipsalliance/chisel3/pull/2912#issuecomment-1366303618) from @ekiwi: > How is this message supposed to be displayed by different backends like SymbiYosys or Jasper Gold? The...
We need to publish CDE to maven, which makes RocketChip and other repository being able to use this without compiling from source, I have added the publish CI infrastructure, beside...
We are working on an open source multiple lane RVV for HPC market https://github.com/chipsalliance/t1 with intensive chaining support. To provide as much as possible memory bandwidth. We don’t support mmu...
In #511, we are struggling to deliver a flow to shrink gds, which is an unexpected flow in physical design flow, but physical design always has such flows for special...