Jiuyang Liu

### Contributor Checklist - [ ] Did you add Scaladoc to every public function/method? - [ ] Did you add at least one test demonstrating the PR? - [ ]...

**Type of issue**: Feature Request **Is your feature request related to a problem? Please describe.** The common metadatas for Synthesis and P&R is required for ASIC designs, Chisel doesn't provide...

### Contributor Checklist - [ ] Did you add Scaladoc to every public function/method? - [ ] Did you add at least one test demonstrating the PR? - [ ]...

### Contributor Checklist - [ ] Did you add Scaladoc to every public function/method? - [ ] Did you add at least one test demonstrating the PR? - [ ]...

#### Related PRs / Issues #### UI / API Impact #### Verilog / AGFI Compatibility ### Contributor Checklist - [ ] Is this PR's title suitable for inclusion in the...

Rocket-Chip Splitting Progress and Notes

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This issue is used to record how I try to split RC into small different repositories, get rid of the cyclic dependencies, make modules as small as possible to make...

**Related issue**: chipsalliance/chisel3#2723 **Type of change**: bump **Impact**: no functional change **Development Phase**: implementation

bump env

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I'm experimentally compiling this repository with clang to slim rocket-chip CI. need this bump to make it compatible to clang.

[Panama] Request to bind InstanceGraph API from CIRCT.

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**Type of issue**: Feature Request After reviewing the current OM C-API. I suggest introducing the `InstanceGraph` Binding from CIRCT. It should expose the `InstanceGraph` result to Scala. Basically the current...