Jiuyang Liu

Results 142 issues of Jiuyang Liu

asap7 introduced multi-VT libraries(SLVT, LVT, RVT). genus will synthesis a verilog file into multi-VT for better optimizations. However SRAM library equals to multi-VT, which made synthesis tool map rtl with...

The Current ClockGroup API is misleading and is strange design pattern for clock doamins. This PR is used for purging out all the ClockGroup usage in rocket-chip, providing a clean...

I wanna use vcdrom with FST, is there any plan to it?

question

These days I did some code review on `Elements` operators. The original idea was trying to solve the the Intellij highlight issue. But I encountered some strange designs which need...

**Type of issue**: Feature Request **Describe the solution you'd like** Queue API doesn't return the Instance of Queue, which makes user impossible to access the Queue instance to `suggestName`. This...

**Type of issue**: Feature Request For a `FixedIOModule`, the `ioGenerator` is its header. Think about this scenario, Different teams can only access the header for different purpose, e.g. RTL designer,...

Prepare for Chisel plugin. ### Contributor Checklist - [ ] Did you add Scaladoc to every public function/method? - [ ] Did you add at least one test demonstrating the...

In this PR, I'm going to add a new Phase of ChiselPlugin to create `SomeSerializableModuleGenerator` object for `SomeSerializableModule` which extends from a `SerializableModule[SomeSerializableModuleParameter]` which contains an main function to elaborate...

- **minimal reproduce Nested Instantiate bug** - **expose cache and elaborated defination to inner defination** - **clean up and refactor SerializableModuleGenerator** ### Contributor Checklist - [ ] Did you add...

API Modification

# TL;DL This is designed for chisel linking flow. - Chisel doesn't need to import `mlirbc`, but need to expose a linkable module to be `FixedIOIntrinsicModuleGenerator`. - `FixedIOIntrinsicModuleGenerator` contains the...