[proposal] add reference sail implementation for each instruction

[sequencer]

In our downstream repository: https://github.com/chipsalliance/rvdecoderdb/pull/39 We are experimenting with adding a sail code snippet for each single instruction, for example: https://github.com/rez5427/rvdecoderdb/blob/sailcodegen/rvdecoderdbtest/jvm/src/sail/inst/rv_i/addi We are wondering would it be possible for riscv-opcodes accepting this try as the upstream? I personally think this can be used for representing the details semantics of each instructions but with some limitations: For instructions w/o architecture state changes, e.g wfi, they should be left empty with an external C-API call. For institutions without a deterministic execution result, a reference implementation would be added but can be overridden by downstream user, e.g. vector fp reduce add. For instructions leading to change the memory state, e.g load store, the implementation should have the C-API inside which for avoiding concrete implementation.

The codegen emulator can be maintained in the downstream repositories to save the maintenance burden for this project.