Rose Thompson
Rose Thompson
Progress made with PR #802.
Resolved in a feature branch ahbopt. Improved Arty A7 clock speed from 20 Mhz to 25 MHz. However, we are saving this for after tag 1.0 as this change won't...
The branch is ahbopt.
Also update fpgaTop.v to fpgatopvcu.sv
I am making notes here so I don't lose this data. I am currently unable to replicate this branch predictor issue. I ran the branch embench benchmarks on commits from...
This is a temp file and should be removed. linux/buildroot-packages/fpga-axi-sdc/fpga-axi-sdc.mk~
fpga/generator/wave_config.wcfg is very out of date. It is used for arranging signals in the ILA waveform viewer. It was generated by vivado and I can't see why it would need...
There is also another issue here. The SPI module isn't working over 5Mhz on the Arty A7. I believe the underlying issue is how the SPIIn is sampled by PCLK...
We are still having issues with SPI. There are still have a few times when SPIOUT is transmitte don the wrong PCLK edge and as I've developing the fpga ImperasDV...
I believe PR #1052 solves this issue, but does not prove that is fixes the problem.