Rose Thompson
Rose Thompson
Resolved with the new SPI module.
I'm happy with these changes. I may have to refactor a few things after the merge to get fpga rvvi in simulation again, but that's is ok with me.
@jordancarlin Can you resolve the merge conflict in wally.do? Then we can merge. My apologizes for taking so long to review this pull request.
Confirmed this is a bug. I extended the hptwAccessFault.S test to create the specific condition above and the HPTW walks the page table multiple times while the IFU stalls the...
I have several thoughts about how to fix this. 1. Easy. We an ignore since the bug is only performance. 2. Simple. Use CommittedF to keep the hptw FSM in...
This is the unused code from the IFU. Lines 214 to 215. ``` logic IgnoreRequest; // *** unused; RT: is this a bug or delete? assign IgnoreRequest = ITLBMissF |...
In lrsc.sv Line 48. ` // possible bug: *** double check if PreLSURWM needs to be flushed by ignorerequest.`
IgnoreRequest's purpose is to flush the cache/bus/dtim request as if it was a pipeline FlushW when the I/DTLB misses and the HPTW makes requests to the LSU. It also checks...
Pull request #1004 resolves my questions about IgnoreRequest.
This was fixed a while ago, but there isn't a test to show that is works.