Rose Thompson

Consolidate testbenches and scripts

1

Reduce the redundancy with the remaining test benches and scripts.

Create an automated FPGA build and run environment which continuously updates the FPGA and runs SPEC 2017 to validate performance.

Make FPGA IP names match figure 23.3

1

After the ecen4243 finishes on May 10 update the FPGA IP module names to match the names in chapter 23.

Branch Predictor Performance Issue

3

Changes since Dec 18, 2023 result in lower branch predictor accuracy by 1 to 2%. We must resolve before TLR5 is completed.

This script is no longer working since our updates to the simulation scripts. We need to update the script to work with vsim and the updated directory structure.

Currently, the Makefile in sim has a specific target for Questa coverage. We would like to move this into the questa sub directory. Ideally any simulator specific config, build targets,...

Remove Hardcoded Paths

1

There are still several locations in the scripts with hardcoded paths specific to either HMC or OSU servers. I'm going to use this issue to track these locations until they...

RAS return after return bug

1

RAS does not correctly handle consecutive returns.

Review SPI clock modes

5

Jacob implemented SPI on the FPGA and found issues with the SPI phase and polarity controls. Need to verify these are all correct.

Concurrent HPTW access fault with IFU bus fetch

2

Issue #412 exposed a bug in Wally with a concurrent I$ miss and DTLB miss. The HPTW makes a request which generates an access fault during an inflight I$ bus...