Rose Thompson
Rose Thompson
Added tests with pull request #981
This sounds like a tricky one to debug. I will try to reproduce on my end with the VCU108 board so we can have more debug signals. I'm very concerned...
Interesting this isn't reproducing on the vcu108. I tried playing around with various baud rates. I'm trying the Arty A7 now. If I had to guess you probably found a...
I am able to reproduce on the Arty A7 but the VCU108 is not triggering the bug unfortunately. I'm working on an ILA script to debug right now.
It's not too unreasonable to think it could depend on the FPGA because the two FPGAs have different hardware configuration. The Arty A7 has a 20Mhz clock and 256MiB DDR3...
Interesting the uart's INTR bit is always high. This is causing the OS to take a trap back into the trap handler immediately on exiting starving all other processes.
Even more interesting the CPU is waiting on a wfi instruction while INTR is high.
That part I haven't reproduced. I've been using screen and it's not rebooting the CPU. What is the tio command you are using?
I think the problem is with either 1. How the driver is claiming the external interrupt. The plic's intIntProgress bit 10 (UART interrupt) never goes low. 2. Or the hardware...
Interesting. I've narrowed the failure down to this section of kernel code. ``` ffffffff801d3844 : ffffffff801d3844: 1141 addi sp,sp,-16 ffffffff801d3846: e422 sd s0,8(sp) ffffffff801d3848: 0800 addi s0,sp,16 ffffffff801d384a: 0140000f fence...