Rose Thompson

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Reopen until we show this is no longer an issue with FPGA lockstep.

This also fails with yosys. @infinitymdm has another implementation that works with yosys; however, the implementation is not as compact. @infinitymdm can you post your solution so we can compare.

Hi @infinitymdm Yes let's reopen your PR and I think we will go ahead and merge it.

Reopening. Issue #1469 shows it is not just yosys which has issues with while loop synthesis.

@infinitymdm Can you resolve the merge conflict and then add the old version as a comment with a short explanation for why we cannot use it. Something like this synthesizes...