Rose Thompson
Rose Thompson
A couple interesting things to note. The two threads accessing the above function only experience the failure if the ld at ffffffff801d3856 effective address is specific number of bytes apart....
I have a hypothesis. I bet the hptw messes up during an interrupt (or similar) and the address translation for the claim data which should we written to the plic...
You might have an older device tree. The current device trees configures 256MiB for the Arty and 2GiB for the VCU108. The fpga/generator/Makefile modifies the zero stage bootloader to accommodate...
Crud this is a problem. I'm going to help Lee reinstall the toolchain next week. Do you have a suggested interrum solution?
@Zain2050 Can you include the elf so I can reproduce the bug? I bet I can debug this really fast if I have the elf.
Hi Mats Brorsson. It shouldn't be too much effort to port Wally to the Genesys 2 board. I just got my hands on one of these boards last week and...
I ported Wally to the genesys II board this morning with PR #1438
@eroom1966 I think this might come down to how the spec is interpreted. > Zicclsm Misaligned loads and stores to main memory regions with both the cacheability and coherence PMAs...
My attempt to generate the debug database resulted in a segfault. I added this to the vlog command. +define+IDV_INCLUDE_TRACE2BIN and set this variable before calling questa. IMPERAS_RVVI_DEBUG=1 ``` # Platform...
[tlbMisaligned.tar.gz](https://github.com/user-attachments/files/17365770/tlbMisaligned.tar.gz)