riscv-perf-model
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riscv-software-src
Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model
Add vector sequencer and execution support for the vector reduction instructions. At least 1 test should be added with an instruction from each category to verify proper sequencing. - [...
Found an interesting case where the model stopped making forward progress and terminated indicating a complete run. I tried to debug and found that the STF read did not reach...
I have identified a bug in the model where SYS instructions flushing from ROB do not prevent further retires in same cycle causing program order assertion Here is the test...
This is the draft PR for the implementation of branch prediction unit.
Hi Arup and Knute, after I talked with Arup, I decided to implement store buffer first to enable data forwarding and then implement multi pipelines. Here is the draft pull....
Working with the previous Rename code base illustrated a series design issues that I needed to address. In this PR, I've changed Rename to support the following: - Move elimination...
This is the design document for the branch prediction unit to be added to Olympia simulator. This document aims to give an overview of the micro-architectural and implementation detail of...
I'm proposing a common design document template in adoc format. We have use of this in internship work and for documenting development in advance of coding. This issue records the...
Moved to _almost_ the tip of Mavis. The head of Mavis requires c++23 features (@bdutro) which we might not be ready for yet. Started to deprecate the use of nlohmann::json...
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Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model