riscv-perf-model
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riscv-software-src
Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model
Implemented: - adds slicing the workloads using the simpointed output - builds olympia inside docker. - refactor for DockerOrchesterator (host) and run_command on container - unfiy redundant functions and remove...
Added documention on how to use trace archive together with RClone
Extended Olympia to support vector load and store instructions. Extend the current LSU so that it can "unroll" a vector instruction and generate separate memory accesses for each active vector...
Currently, the way the lsu replay works is that when a load is issued to the lsu pipe but it is not ready because of a cache miss, it is...
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Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model