circt
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llvm
Circuit IR Compilers and Tools
This PR (separated from https://github.com/llvm/circt/pull/6977) implements ExportVerilog support of sv.func, sv.func.call.import, sv.func.call and sv.func.call.procedural.
This is separated from https://github.com/llvm/circt/pull/6977. This changes pre-passes for ExportVerilog to run on HWModuleLike instead of HWModuleOp. https://github.com/llvm/circt/pull/6977 is going to add a support for SV func op and legalization...
Given all the talk about the mistake of conflating symbols with names, I had assumed that this had been fixed in the HW dialect. Is there some reason it hasn't?...
``` hw.module.extern @foo(in %t "h ^hello" : i32) ``` is printed by circt-opt as ``` hw.module.extern @foo(in %h ^hello : i32) ``` which is not valid. I may try to...
Quite a few of our dialects define a `ClockEdgeAttr` to allow ops to specify which clock edge they are sensitive to, such as `posedge`, `negedge`, and both `edge`s. It would...
So, I've taken a closer look at this again following the discussion in #7022 and it turns out that there were CMake options added to support this for types and...
Currently, https://github.com/llvm/circt/blob/main/lib/Dialect/ESI/runtime/CMakeLists.txt is written in such a way that (i presume) it's expected to be added via `add_subdirectory`. Instead, I think it would be better to have an `esi.cmake` file...
- Adds basic Assertion support to ARC - Fixes: https://github.com/llvm/circt/issues/6810 We will implement this in two steps: - [ ] Support the `assert` operation in Arc by adding `arc.assert`, and...
With input probes no longer being valid IR, this pass can be simplified. Paths are now append-only and can be resolved in a single post-order (considering all entry points /...
