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Circuit IR Compilers and Tools
We are getting things like: ``` %c0_ui2 = firrtl.constant 0 : !firrtl.uint {name = "_count_reg_32_redundantReg_r_wrappedData"} %c0_ui4 = firrtl.constant 0 : !firrtl.uint {name = "_count_reg_16_redundantReg_r_wrappedData"} %c0_ui1 = firrtl.constant 0 : !firrtl.uint...
In bea85107e8e42261e9c2e3ed24dd398e7f33b915 we had to revert #6719. This change caused some memories that were previously targeted from OMIR to fail in the EmitOMIR pass. Opening this issue for tracking the...
Consider this snippet, created while trying to reduce example in #7050: ```mlir module attributes {calyx.entrypoint = "main"} { calyx.component @main(%go: i1 {go}, %clk: i1 {clk}, %reset: i1 {reset}) -> (%done:...
While the [documentation](https://mlir.llvm.org/getting_started/Debugging/#detecting-invalid-api-usage) states that there might be false positives, I think it might be worth a look into the individual test cases and patterns. If there are no false...
This PR addressess issue [#6913](https://github.com/llvm/circt/issues/6913) to enable the support of attributes in the SMTLIB export pass.
Add small test for load-bearing "UNR" behavior especially interaction with `--add-companion-assume`.
Detected by -DMLIR_ENABLE_EXPENSIVE_PATTERN_API_CHECKS=ON. cc #7047.
The current SVModuleOp does not provide port lists and instanceOp can not establish a connection between SV modules. They completely do not meet growing demand in Moore (`circt-verilog` frontend) dialect....
Script to help us/developers check this more easily themselves (some amount of `-P0 -n20` or something to xargs helps make that fast, or thereabouts). Add CI step that runs this.
Verifier checks that else region is non-empty if present. Current patterns can fail this verification, for example when the else region contains some control op that removes itself (`emptyControl`) the...