circt
circt copied to clipboard
llvm
Circuit IR Compilers and Tools
Fix `inferReturnTypes` impl to use adaptor to fix with properties.
e.g., https://github.com/llvm/circt/actions/runs/6043597331 Current run presently has 30 minutes but probably won't make it either: https://github.com/llvm/circt/actions/runs/6048085800/job/16412795947 . If the bisect hits the time limit in the interesting cases, may not be...
InnerSymAttr verification (sanity checking the symbols) is performed for operations (InnerSymOpInterface's verify) defining inner symbols, but symbols on ports are not checked. They are checked to not be duplicates as...
IR lowered from following chisel has deeply-nested if operation with 2^14 depth. It causes stackoverflow in MLIR verifier (and parser if we use textual format of MLIR). Bytecode seems working....
This PR introduces DPI import and call operations. To import a function, the following can be declared at the module level: ```sv.dpi.import @test(%arg0: i32) -> (res0: i5, res1: i6)``` This...
If we want to allow passes to run after ExportVerilog (e.g. to analyze the actual names assigned in ExportVerilog), ExportVerilog needs to ignore unknown ops instead of producing an error....
I've been messing around with FIRRTL attach operations nested in `WhenOp` regions fully expecting them to be illegal. After all Chisel refuses to produce them. But, after careful reading of...
FIRRTL memories that do not go through the `--repl-seq-mem` path to replace them with blackboxes always produce a wrapper module around the memory. However, this can result in poorer performance...
`module(input : bundle` should be transformed to `module(output : bundle`
A well-documented Firtool-lib C-API would be great for downstreams (e.g. `chisel`) references. There is a lack of such a thing at the moment. So I opened the issue to discuss...
