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Circuit IR Compilers and Tools
Prevent `hw.array_get` operations from exceeding their memory bounds after lowering to LLVM. This adds a dynamic check to the index operand (if required) which can invoke a handler function to...
Adds lowering patterns for `handshake.pack/unpack` to DC. For the actual (data-side) tuple operations, `hw.struct`s are used. This is purely for pragmatic reasons; Firstly, `hw.struct` is for all intents and purposes...
This PR makes the undocumented support of i0 in comb official by removing the documentation stating it is not supported and adding a few tests to the canonicalizer (and marginally...
This is the second patch stacking on #6952 This patch tries to legalize `AddFOp` and support floating point `SeqMemory` read/write in SCFToCalyx.
The current structure of the `verif` dialect requires the use of `ltl.clock` to associate a clock to an assertion (which is required). This means that a use-def analysis is required...
Handle conditional operator `?:`. Use `scf.if` to control the selection of expressions, and return the selected value through `scf.yield`.
# Summary Using printf strings to encode verification operations is deprecated. This is a transparent change to Chisel users, as Chisel no longer uses this for assert/assume/cover. For the deprecation...
```mlir hw.module @Baz(in %cond : i2, in %value : i2, out o1: i2, out o2: i2) { %0 = comb.and bin %cond, %value : i2 %1 = comb.and bin %0,...
InlineModules pass currently strips inner symbols so it could break design. ```mlir $ cat test.mlir hw.hierpath @hier [@Foo::@bar, @Bar::@a] hw.module private @Bar(in %a : i1 {hw.exportPort = #hw}, out b...
When I write a FIRRTL program like this: ``` circuit FormalSimple : module FormalSimple : input clock : Clock input reset1 : UInt output io : UInt wire a1 :...
