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Circuit IR Compilers and Tools

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## Overview This patch is the first one of a sequence of future PRs that will try to support a complete pipeline from PyTorch Add operation to FPGA. The lowering...

The move to using `InnerSymAttr` in https://github.com/llvm/circt/pull/5703 broke a somewhat obscure usage of the Python API for creating `hw.WireOp`s directly. The old code used to look like this: ```python op...

Array get/slice lowering patterns in HW-to-LLVM generate unguarded loads, potentially loading values from invalid memory locations: https://github.com/llvm/circt/blob/ce9877c55544937aec68b2a5b099ccef788168ba/lib/Conversion/HWToLLVM/HWToLLVM.cpp#L136-L176 In case the index is not a power of two, we should probably...

bug
HW

We are probably abusing canonicalizations to implement optimizations which should really be in some sort of `optimize-comb` pass. Canonizations should really just be simple transformations which aid analysis. So we...

Comb

Consider the following: ```scala //> using scala "2.13.12" //> using repository sonatype-s01:snapshots //> using dep "org.chipsalliance::chisel::7.0.0-M1+74-3c558514-SNAPSHOT" //> using plugin "org.chipsalliance:::chisel-plugin::7.0.0-M1+74-3c558514-SNAPSHOT" //> using options "-unchecked", "-deprecation", "-language:reflectiveCalls", "-feature", "-Xcheckinit", "-Xfatal-warnings", "-Ymacro-annotations"...

I'm trying to install a Python module which requires `circt==1.48.1.dev34`: ``` ERROR: Could not find a version that satisfies the requirement circt==1.48.1.dev34 (from magma-lang) (from versions: none) ERROR: No matching...

Dedup will now print what modules deduplicate when running with `--debug-only=firrtl-dedup`: ``` FIRRTL Deduplication: - dedup "B_" into "B" - dedup "A_" into "A" ```

The SMT operations `smt.forall` and `smt.exists` support attributes called `weight` and `no_pattern` to give hints to the solver backend (e.g., Z3). We should add support for them in the `ExportSMTLIB`...

good first issue

We are missing an optimization to build reduction ops when possible. Consider the following which is doing `b[0] | b[1]`: ```mlir module { hw.module @Foo(%a: i1, %b: i2) -> (c:...

enhancement
good first issue
Comb