circt
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llvm
Circuit IR Compilers and Tools
# Context Platform: macOS 14.1.1 Architecture: arm64 circt version: Firtool 1.58.0 release, also f124fb041 # Description When generating a design from Chisel with arrays of SRAM instances, I notice that...
MLIR has a debuginfo stripping pass, use it to strip location information instead of our own pass. Possible push the parameterized version upstream.
Follow-up on #6388/#6416 The merged PR hotfixes the crash during compilation, but there remain inconsistencies in the serialized output format. Pushing the example of #6388 through `circt-opt --mlir-print-debuginfo --mlir-print-local-scope` prints:...
Fixes #6360. --- The first fix #6339 (reverted) caused a regression reported in #6360. In the first try, I forgot to handle the bit extract operation that follows it, the...
Here's the simplest example I came up with: ``` FIRRTL version 3.3.0 circuit Top : module Top : skip class MyClass : output out : Integer propassign out, out ```...
Support member-access expression. Add container multiSymbolValue for multi-symbols pointing one value.
This PR adds the ops that were missing to allow us to basically model all of SVA with LTL. This is justified in [this design doc](https://docs.google.com/document/d/19Mbh0NHDRAwovj6bsiUcVX7NayZTVG5C9dgiKPM2XUY/edit?usp=sharing) and [this SVA summary...
This PR is in response to #6982 and adds clocked versions of assert, assume, cover. What still needs to be done: - [x] Update ExportVerilog - [x] Add Verifier that...
This PR fixes a regression caused by PortAnnotation mutation. We have to batch-update the port annotations to avoid compile time regression. Several other improves are added along with the fix:...
