Complete testing for unpacked arrays in generated SystemVerilog

[mkorbel1]

Motivation

There are known bugs with "unpacked" arrays in SystemVerilog. For example:

• Assigning:
  • https://github.com/steveicarus/iverilog/issues/482
  • https://github.com/verilator/verilator/issues/2907
• Single-element unpacked:
  • https://github.com/steveicarus/iverilog/issues/915

The ROHD test-suite relies on SystemVerilog simulators to verify the generated output. These bugs in SystemVerilog potentially leave a validation gap in generated verilog.

Desired solution

Follow-up with bug reports on SystemVerilog simulators and test ROHD against them as fixes are released.

Alternatives considered

No response

Additional details

No response