Make "expected" message in SV testbench from SimCompare include width for invalid signals

[mkorbel1]

Motivation

The SimCompare utility generates messages like "expected y=1'bx but found..." in the generated SV testbenches. This is inaccurate for multi-bit invalid signals. This is not a functional problem, just to make the print message nicer.

Desired solution

Print a message that includes width, if applicable, or omits the width, but not the incorrect width.

Alternatives considered

No response

Additional details

No response