stnolting

You are really hard-working! ;) What do you think about keeping all the makefiles at first until the documentation (especially the READMEs) is updated to use pydoit?

I totally agree and I am really looking forward to have a unified execution system. All those makefiles are (annoying) to maintain and document... I am just worried that we...

@umarcor Since we have `neorv32-setups` now this seems to be outdated and we can close this?! 🤔

I need to check that out. Can you say something about the "code quality" of the verilog code generated by GHDL or yosys? I think it would be nice to...

> Implementation should be as easy as adding the following target to [neorv32-setups: osflow/synthesis.mk](https://github.com/stnolting/neorv32-setups/blob/main/osflow/synthesis.mk): > [...] > I'm unsure about the following (would be an interesting experiment to have some...

I am tinkering with the NEORV32 as plain Verilog netlist. I have tested the version using GHDL `synth` as well as the GHDL/GHDL-Yosys approach. :tada: The "straightforward" GHDL/Yosys approach does...

For the records 😉 * [neorv32-verilog](https://github.com/stnolting/neorv32-verilog) repository * [icarus-verilog-prebuilt](https://github.com/stnolting/icarus-verilog-prebuilt) repository

That looks great! I will have a closer look. But still I cannot find the actual HDL files!? 🤔

Hey there! > I would like to run freertos application with this soc but I can not find the instruction/examples. There are no instructions or examples yet. However, running FreeRTOS...

I have to admit this might not be the most elegant way to initialize the ROM. > * Use a VHDL function for initialising a ROM from a bin or...