stnolting

You are right! Something was wrong there... I have fixed that and updated the repository. Tanks for the hint!

Sorry for the late answer. > The current implementation of neo430_bswap seems to be buggy. In my case, the compiler selected a totally unrelated register to call swpb on (not...

> In the neo430 Xmen .vhd , we knows 1x16bit splite to 2x8bit , but why the WEbit is 2bit ? I see the RTL, Xmem's R/W_ADDR was connect to...

Hey Andreas, sorry for the delay... Unfortunately, there is no more sophisticated testbench available yet. I was thinking about a self-checking TB to verify the correct execution of instructions, but...

I think the label is wrong. Chapter 24 shows a list of all instruction encodings. And there we have a different (the correct) label: 

If I have an architecture where `misa.x` is zero (so no non-standard extensions), I *can* assume that all non-implemented instruction trigger an illegal instruction exception, right? Anyway, if I cannot...

@jscheid-ventana Thanks for the information! I already saw recent development that goes in this direction in #697

@ObiWanRohan Btw, there is a `time` CSR (or two CSRs `time` and `timeh` on rv32, respectively): > The time CSR is a read-only shadow of the memory-mapped mtime register. [3.1.11...

Hey there! > we picked IBEX CPU from lowRISC I also like lowRISC. Ibex is a really great core! :+1: > Does NEORV32 have any verification TB (other than simple...

Sorry for the late reply... I do not have a real background in verification, so setting up a self-checking testbench was the best I could come up with. Recently, I...