stnolting

Hey everyone! Burst accesses would be a great thing to have! My current evaluation setup uses an external DDR RAM, which is horrible slow when using single accesses. Hence, I...

> That is true. I think the best option would be to let the bus slave assume a specific burst mode. Meaning a FIFO or register may assume that a...

> The main advantages from my biased point of view are reducing the load on the instruction fetch channel That's true! In its best case, this instruction saves up to...

~For the records: this is being discussed in https://github.com/stnolting/neorv32/issues/633#issuecomment-1604684303~

Oh sorry, seems like I have mixed up something 😅 `B` vs. `Zb*` is something I need to take care of because the `B` extensions basically does not exist (anymore):...

The `B` ISA extension has been ratified in April 2024 (https://wiki.riscv.org/display/HOME/Ratified+Extensions). It consists of the `Zba`, `Zbb` and `Zbs` sub-extensions, which is/are implemented by the core (see https://github.com/stnolting/neorv32/pull/869). So I...

Hey Bob! Finally, I have time to come back to this 🙈 I really like the concept of the "compressed" address space. But I am not sure how to integrate...

I have been thinking about simplifying the address space and decoding... Right now the address space of the IO modules / peripheral is densely packed making it hard to add...

Hey there! This looks really promising! Unfortunately, my Python capabilities are quite limited, so it'll take a while for me to understand your script :wink: I see a general problem...

> my python skills are also quite limited; i only picked python because i found other .py files in the project.... my preferred scripting language is node.js, if that helps.......