stnolting

Hey @biosbob! This PR has been pending for way too long... sorry for that 🙈 How about refreshing this? I think it would be really handy if we could provide...

Hey @Unike267. > The final goal is connect to NEORV32 a parametric and configurable hardware circuit which implements multiple activation functions (Sigmoid, Tanh, ReLu, Leaky ReLu etc.) to accelerate computations...

Sorry for the late response.. > Yes, of course, the application is hyper-spectral image processing. In short, we have a Photonfocus camera, integrating imec’s hyperspectral sensor. That's a cool project!...

> Normally we had the .f file(s) in parallel with the RTL files, or if you have a lot of sub-dirs for RTL functions at the root. In our case...

> We get some odd-ball parsing errors (e.g. use string types) that was root-caused to be caused be the move away from component declarations in the code base (A move...

That would be a really cool feature, I think. It would make setting up the rtl files much easier and we could finally drop all the hard-to-follow hierarchy stuff in...

Yes they are: ``` ISA: RV32IMCUZicsr_Zifencei_Zba_Zbb_Zbc_Zbs ``` For example, these ISA extensions are used by this port of RISCOF: https://github.com/stnolting/neorv32-riscof/blob/6aba719d8fe7f0ff6bf80743b0b76aa55ef8b098/plugin-neorv32/neorv32_isa.yaml#L4

Hey @timaosan! First of all, the memory modules from [`neorv32/rtl/core/mem`](https://github.com/stnolting/neorv32/tree/main/rtl/core/mem) were designed in a platform-agnostic way. So they can (_should_) be synthesized for any platform resulting in the correct inference...

Are there any updates on this? Otherwise we can close this (for now :wink:).

Great idea! Let's keep this open until the next toolchain upload.