stnolting

@juanmard I am working through this setup right now https://github.com/juanmard/neorv32/blob/fomu-serial/setups/examples/neorv32_Fomu_BoardTop_MixedLanguage.vhd trying to port that to my "Frankestein UPduino USB" setup :smile: Just some questions: * Have you tested that on...

@umarcor As far as I understand, https://github.com/no2fpga/no2muacm is a hardware PHY and a RISC-V core for all the USB stack handling. This could be ported to the NEORV32, but that...

@umarcor > Anyway, let's see if the timing results with usbserial are good enough! As you said, Juanma had it almost done! 👍 Fingers crossed!! :wink: > The physical one...

I made some more tests with https://github.com/davidthings/tinyfpga_bx_usbserial and finally I came up with a setup on my UPduino board that is "working" 🎉 😄 #### The Setup I am using...

> They changed the names (and sometime there is no equivalent at all) of all the primitives, the the no2muacm pre-built netlist is full of SB_LUT4 / SB_CARRY / ......

> Feel free to pick the sources in https://github.com/VUnit/vunit/tree/master/examples/vhdl/array_axis_vcs/src and adapt them to your own needs. Thanks for the hint! Is this intended for synthesis and for arbitrarily-related clocks? Seems...

Just for the records: -> https://github.com/stnolting/neorv32/discussions/113 :rocket: :wink:

> A FIFO is an adaptor for clock domain crossing per se. If one clock is used for writing and a different clock is used for reading, the FIFO is...

> Hence, I would suggest keeping it simple for now. Let's have a single visible AXI Stream (actually, two, one in each direction). We can use multiple channels through the...

> For now, I think we should avoid 2, precisely because it requires DEST and the interconnect. I suggest implementing 1 first, and discussing the port naming/types for 3. I...