neorv32

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@google provides some kind of framework with their CFU-Playground to add custom instructions to a RISC-V design. There is no real description of the interface, latency, et.c in their repo (at least if have found none) but it seems like @grayresearch has drafted some general specifications in https://github.com/grayresearch/CFU.

Does anyone know of real CFU implementations? The one(s) in the CFU-Playground repository are just exemplary. I would like to check those CFUs for interoperability with the recent NEORV32 Zfxcfu ISA extension update (#264).

@stnolting did you see https://cfu-playground.readthedocs.io/en/latest/projects/mnv2_first.html ?

@tcal-x @mithro @kgugala are you aware of other open source CFUs?

That looks great! I will have a closer look. But still I cannot find the actual HDL files!? 🤔

That looks great! I will have a closer look. But still I cannot find the actual HDL files!? 🤔

I believe it's Migen, so you need to generate/export the HDL (Verilog). However, you can do it once, and then deal with the Verilog as if it was handwritten.