stnolting

Hey @mlapaj, sounds good - I always wanted to play with those FPGAs. > Can I prepare such example setup for this ? That would be really great!

Wow, that looks great! Thanks for sharing! I'm curious as I have never worked with these FPGAs (yet). Could you say something about resource utilization and clock speed? How about...

> With the latest commit I have added info abut clock, basically I used 27 MHZ - default clock frequency taken from crystal oscillator Thanks for the update! > Also...

So you want to read whole sector from SD card with minimal CPU interaction, right? With the current set of features this is what I would (quite naively) do: *...

> So to summarize, I guess the most general solution would be to just have more (maybe even a configurable number of) DMA channels. With 2 channels the SPI use...

Right, I really like this concept. You could add another field for a "pointer" and then put as many descriptors into RAM as you like and "chain" them to execute...

> But i mean when the system designer decides to use an DMA, then i think he has to take in mind that's in general is a second processor. True,...

Isn't there something missing? The variables for the return data?? ```c neorv32_cfu_r3_instr(0b1111111, 0b001, fir, 0); neorv32_cpu_csr_read(CSR_MCYCLE); ``` The cycle counter will increment in every clock cycle if the CPU is...

> Since the vcd format cannot display type elements I've made the following assignment: That's smart! > At first look, it seems that both instructions take the same time to...

> In view of these results, we can confirm that the latency measurement through CSR(MCYCLE) adds one extra cycle to whatever we want to measure between csrw(mcycle = 0) and...