Damien Pretet
Damien Pretet
Timeout detection and management can be enabled and configured by interface. This avoids any deadlock if a slave doesn't respond to a request, or if a master doesn't accept a...
This branch contains updates in memfy and dcache to support concurrent read/write access if no address collision can occur. The updates are the following: - memfy: `AXI_ORDERING` parameter set to...
To improve overall system performance, an AXI intermediate component can issue a write response before the request reaches the destination. From AMBA AXI specification: > Response before the endpoint To...
In order to save area, a master or slave interface could be write-only or read-only. If all the masters agents are write-only or read-only, the switches and masters interfaces can...
In order to help debugging and tracing, the core could embed a queue, fed by the master and the slave interfaces, to stream out some events like: - 4 KB...
In order to widely support feature #12 easily, a basic RTL generator must be developed to drop the top level code. It must generate the top level with any number...
Today, the core supports 4 slave and 4 master interfaces. The arbiter has been designed to support up to 8 agents. The top level could be rewritten to support any...
The core currently doesn't support correctly AMBA completion ordering rules if a master issues multiples outstanding requests with the same ID among different slaves. To address the limitation, an `axicb_slv_switch`...
Some interconnect topologies are the combination of multiple AXI4 sub-systems. All these sub-system have their own memory map, which may not match the overall address ranges of the global system....
Today the core supports fixed priority level to route the traffic across the infrastructure. By the use of `AQOS`, the arbiters could better manage the QoS. The QoS across the...