CyrIng

> Sure Thank you. Can you switch to the [`develop`](https://github.com/cyring/CoreFreq/tree/develop) branch and pull latest commit 7ee38f9284dfa830ccae73728dd7dce40bc0b03a which queries IOMMU `[1022:14d9]` from Raphael list Make sure to unload previous version. Next,...

@nooberfsh Thanks. * DDR size is still a work in progress * AMD-V and IO/MMU are now showing up * `TSME` has toggled to enabled since your previous output. I'm...

> ``` > tom@arch ~/h/p/CoreFreq ((7ee38f92))> sudo rdmsr -ax 0xc00110e3 > 610bae00bc800000 > ``` Although register is accessible and `SuppressBPOnNonBr` bit is clear, I'm finding no specification update about such...

Contributors @leinardi [5800X] @LethalManBoob [5800X] [5700X] @thor2002ro [5900X] @Slaviusz [5950X] @WildPenquin [5950X] @ppascher [5950X] @olejon [5950X] @Jon0 [7950X] @KeithMyers [7950X] @amfern [7950X] @tofurky [7950X] @mikealanni [7945X] @madoverlord40 [9950X] VCO change...

>> Please post screenshots of the UI View > Sensors > Voltage in various cases: Idle and Stressed CPU (not showing Menu) > > Do I do this while having...

@madoverlord40 Thank you for your tests. CO is really odd: from idle to stress, the `VID` delta is just about `4` for most cores. And unfortunately `9950X` results don't behave...

> I still have CO on and have not testing with it off but as having curve optimizer on at -20 and level 5 CPU LLC in bios, i dont...

> Ok so i cleaned and rebuilt with make -j HWM_CHIPSET=AMD_VCO > Im using a CO in bios of -20. When CO is activated, the `VID` values in both case,...

Let me show you what we have with Zen2/Matisse 1. **No** voltage optimizer or whatever LLC or performance tricks are activated 2. Only PBO, in its default mode, is allowed...

> You know i think these voltages im getting right now are good, not that i know what the formulas should be. But i rebuilt with just -j on develop,...