CyrIng

Hey, here's my build [procedure](https://gist.github.com/cyring/51a43d71e1dc0ec736c0055b08f438ba)

@BugReporterZ: #486 `12th Gen Intel(R) Core(TM) i7-12700K` ``` Processor [12th Gen Intel(R) Core(TM) i7-12700K] |- Architecture [Alder Lake] |- Vendor ID [GenuineIntel] |- Microcode [0x00000035] |- Signature [ 06_97] |-...

In branch [`develop`](https://github.com/cyring/CoreFreq/tree/develop), commit c376448200f46da0444be3f26d93351a13367137 brings a decoder of the **Meteor Lake** memory controller Decoder has been programmed from the Core Ultra Processor [datasheets](https://www.intel.com/content/www/us/en/products/docs/processors/core/core-technical-resources.html) I will appreciate if anyone could...

@BugReporterZ thanks; it was indeed meant for Meteor Lake I also want to debug previous generations IMC; your output helps a lot but **I need other combinations** of DDR4, DDR5,...

Source: [Intel](https://edc.intel.com/content/www/us/en/design/publications/14th-generation-core-processors-cfg-and-mem-registers/d0-f0-host-bridge-and-dram-controller-mchbar-memory-controller-part-2-registers/)  From `MADCH.DDR_TYPE` we can tell if `LPDDR5` or `DDR5` is set up with [ADL](https://github.com/cyring/CoreFreq/blob/4705b327404ff96fa00736fdad571e4ec5381268/x86_64/corefreqk.c#L6430) and compatible but also [MTL](https://github.com/cyring/CoreFreq/blob/4705b327404ff96fa00736fdad571e4ec5381268/x86_64/corefreqk.c#L6489) ---- Still no clue from register [MAD_DIMM](https://edc.intel.com/content/www/us/en/design/publications/14th-generation-core-processors-cfg-and-mem-registers/channel-0-dimm-characteristics-mad-dimm-ch0-0-0-0-mchbar-offset-d80c/) how...

As shown in MTL datasheet vol 1 

@paulzzh Thank you for your Raptor output I don't have its Memory Controller device identifier. Can you please post the output of the following command: ``` lspci -nn ```

@paulzzh Your `Host bridge [8086:a740]` has been added to probe the Memory Controller You can now pull the [`develop`](https://github.com/cyring/CoreFreq/tree/develop) branch; rebuild and reload _CoreFreq_ (especially its driver `corefreqk.ko`) Can you...

> Where is `Controller #1 DIMMB2` ? It did however with AlderLake & DDR4 https://gist.github.com/cyring/f15646816a47a04f8b8f9c3a4cada24c?permalink_comment_id=4454592#gistcomment-4454592 That's why this issue remains opened: I wish new developers could work straight on HW...

@BugReporterZ Hello, Can you please pull the latest commits from the [`develop`](https://github.com/cyring/CoreFreq/tree/develop) branch and show the output of `corefreq-cli -k -n -B -n -M` ? CC: @paulzzh