CyrIng
CyrIng
@svmlegacy latest code is now available in the development branch. Hope there is no regression on your side and it fixes your current DRAM frequency ?
> Pulled develop up to date as of this afternoon. Still seeing "maximum" DIMM frequency. Thank you. **EDIT**: I'm now able to reproduce the current DRAM frequency issue. I'm not...
@svmlegacy Hello Can you pull and test latest `develop` branch: Register [BIOS DDR Mem Clock](https://github.com/cyring/CoreFreq/blob/287b81caeb27fc31a8c4ca3bc034f8c2751ce35b/intelmsr.h#L2815) (`0x5e00`) which is specified in Haswell is apparently also working on Ivy Bridge:  Remark:...
> Also good on Sandy (Intel Core i7-2600): Thanks for the answer. Meanwhile, I have found the DRAM PLL bit which means frequency is now computed based on BIOS FSB,...
> Changes look good and are valid for my motherboard! Thank you very much helping to improve SNB & IVB. With the new Registers better mastered, I'm now providing same...
@svmlegacy I have back-ported IMC code from HSW Using `develop` branch, you should now read the same geometry on SNB as HSW
@svmlegacy and any Broadwell, Haswell owner: I need to dump Register at MCHBAR address `0x4c00` (_This register is undocumented, so we are reversing in this [header file](https://github.com/cyring/CoreFreq/blob/2fe50f3d859b479b3b54f178d2a4939019663308/intelmsr.h#L3269)_) Based on `develop`...
@svmlegacy : For IMC testing, here's a Haswell/Broadwell development archive. [CoreFreq_develop.tar.gz](https://github.com/cyring/CoreFreq/files/9739853/CoreFreq_develop.tar.gz)
@svmlegacy Hello, Changes are now tracked through a dedicated Haswell, Broadwell branch You just have to pull and build [develop_HSW_BDW](https://github.com/cyring/CoreFreq/tree/develop_HSW_BDW) to test the IMC Thank you
> develop_HSW_BDW branch: Thank you. Can you pull and test `develop_HSW_BDW` in which I'm trying to better estimate the DIMM slots count.