CyrIng
CyrIng
Results from commit 597c0bbc9c87c9c18cef90771f0f127389d4e548 
@svmlegacy Hello, Could you test the `develop` branch with your SandyBridge, IvyBridge and check if third timings are same as BIOS settings ?
@svmlegacy Thank you It's odd, we're not getting the DIMM geometry. I have tested it also with 3770K same Chipset PCI ID as you can see above. I have to...
@svmlegacy I think the missing DIMM topology is due to a regression I have introduced in this commit 977f36efd70276c7f34e663bc0a4975f1510bc4e This was pleasing my IVB 3770K setup (to match with the...
@svmlegacy Hello, Can you test with `develop` branch and show the IMC output? Thank you Remark : there's a geometry regression fix in latest commit.
> Still isn't identifying the current clock rate (1067 MHz), but is pulling the maximum module speed in XMP now (2133 MHz). Is this what you're expecting ? ``` Panther...
@svmlegacy To make things easier, I'm providing this attached version with the debug traces I need [CoreFreq_develop.tar.gz](https://github.com/cyring/CoreFreq/files/9665203/CoreFreq_develop.tar.gz) This version is also making use of a [`DIMM A SELECT`](https://github.com/cyring/CoreFreq/blob/757fc90d04320a9e63da15c84a5a1783914ade5c/intelmsr.h#L3037) bit to...
@svmlegacy Hello, Any chance to get results from above request ? Regards
@svmlegacy > I'm not sure exactly what the bus rate and bus speed should be, but certainly the DDR3 speed should be 1067 MT/s in my case. While my RAM...
@svmlegacy FYI, in the latest archive, above, there is no trace. This version just focuses on providing you the right DRAM frequency. So only the IMC output will be enough....