CyrIng

[WANTED] AMD/Zen3: Cezanne, Rembrandt, Milan, Chagall

14

Hello The targeted processors have a CPUID signature among the following: Architecture |CPUID|Misc|Support|Specs -------------|-----|----|-------|----- `[Zen3/Vermeer]`|`AF_21h`| Ryzen 5950X|[DONE](https://github.com/cyring/CoreFreq/wiki/Ryzen-9-5950X)|`56214-B0-PUB_3.05_PPR.pdf` `[Zen3/Cezanne]`|`AF_50h`| Ryzen APU|[DONE](https://gist.github.com/cyring/c93ab792ee9165cfd287d9f71a62de0d)|`56569-A1-PUB_3.03_ppr.pdf` `[EPYC/Milan]`|`AF_01h`| Genesis[GN]|UNKNOWN|`-` `[EPYC/Milan-X]`|`AF_01h`| EPYC|UNKNOWN|`-` `[Zen3/Chagall]`|`AF_08h`| Ryzen Threadripper|UNKNOWN|`-` `[Zen3/Badami]`|`AF_30h`|[BA] - 7...

[Intel/Haswell/Desktop] Core i5-4570 IMC Timings and DIMM geometry

1

# [`i5-4570`](https://gist.github.com/svmlegacy/729c832d38d879551f8af2050f044a36) ## Timings Setting | _CoreFreq_ | BIOS ----------|------------------|-------- `tRRD` | `5` | `4` `tWR` | N/A | `10` `tFAW` | N/A | `20` `tRTP` | N/A | `5`...

[Intel][IvyBridge] IMC third timings are wrongly decoded

6

Memory controller third timings are wrongly decoded on `Core i7-3770K`  Trying several BIOS values reveals settings are changed in MCHBAR register [`0x4008`](https://github.com/cyring/CoreFreq/blob/0cb1db0ad2a9daaf6e12b1bb1b55743d17584838/intelmsr.h#L2868). Unfortunately specs about this register are reserved;...

In the main widget, press enter to submit a command: the GUI exits with a violation access. It shouldn't be difficult to fix but I'm focusing on CoreFreq project.

''' outl(int fd, unsigned int addr, unsigned int val) { struct iodev_pio_req out={.access=IODEV_PIO_READ ''' IODEV_PIO_WRITE instead of IODEV_PIO_READ

Page Fault in Core2

1

Remove any Turbo MSR read if the processor is a Core2

What steps will reproduce the problem? 1. Using a processor with the Fast-Strings feature is not available 2. Check its value in the SysInfo Widget What is the expected output?...

What steps will reproduce the problem? 1. Run xfreq-intel 2. Run xfreq-gui 3. Invalid values found in the System Information Widget What is the expected output? Same Channels and Timings...

This is impacts &A.configFile and &A.Geometries in main() and LoadSettings()

[Intel: Gen 12,13,14] Memory Controller data

79

Decoder has reporting issues among DDR4 and DDR5, two or four DIMMs, 32 or 64 bits per channel Based on **latest version** `1.97.2`; Owners of Intel Processors of 12th, 13th,...