CyrIng

Hello, We have an issue with Zen4 voltage in discussion #439 Could you join it and post voltage from your Raphael 7950X ? First the output of the general overview...

> Still OK so far with the fix in place. I reloaded k10temp module to see if that changes things. > > Info is here: [#439 (comment)](https://github.com/cyring/CoreFreq/discussions/439#discussioncomment-9874109) Thank you very...

> Sorry to revive an old issue, but I just saw a couple bad max readings that don't appear to be related to a negative number like previously: > >...

Found something from AMD I left in code comments https://github.com/cyring/CoreFreq/blob/5aefb1b6c966f2d1fd973c42e37e7d832c7d5f07/x86_64/corefreqk.c#L16189

[Micron](https://www.mouser.com/datasheet/2/671/24gb_ddr5_sdram_dierevb-3412405.pdf) > Notes: 1. For non-binary densities, a quarter of the row address space is invalid. When the MSB address bit is HIGH, the MSB-1 address must be LOW.

@nooberfsh Thanks for your dump. Unfortunately I'm finding no hint in this register. Can you show me how your 9950X memory controller is decoded with: ``` corefreq-cli -k -n -B...

> Hi. 9950x, 2 * 48G Hello, Can I have this long list of dump registers based on these specifications   ```sh # UMC::BaseAddr ## Channel 0 ./zencli smu...

> Sure, but I can't access my PC until this weekend, I'll post the result as soon as possible. Will you also please have a try to the branch [develop_amd_ext_apic_id](https://github.com/cyring/CoreFreq/tree/develop_amd_ext_apic_id)...

> > > Sure, but I can't access my PC until this weekend, I'll post the result as soon as possible. > > > > > > Will you also...

@nooberfsh Thank you for your answers. * Still analyzing UMC Registers which will take some time. * Can you post the output of `lspci -nn`: I need to probe the...