sv-tests

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Bumps [third_party/tools/yosys-uhdm-plugin-integration](https://github.com/antmicro/yosys-uhdm-plugin-integration) from `71143e7` to `bc99d46`. Commits bc99d46 Remove uhdm.so from install script (#1975) a398dd2 Fix CI for external PRs (#1973) d638a5f Remove uhdm.so from install script 994c452 Perform linguistic...

dependabot[bot]

Bumps [third_party/cores/swerv](https://github.com/chipsalliance/Cores-SweRV) from `ba40194` to `915fb34`. Commits 915fb34 Doc: Update PRM aa0301e Update release notes b0c1071 Review README, standardize syntax. f3407ff Rename to VeeR See full diff in compare view...

dependabot[bot]

Bumps [third_party/tools/synlig](https://github.com/chipsalliance/synlig) from `bd35861` to `fe8f61f`. Commits fe8f61f Build(deps): Bump third_party/surelog from f687293 to 37ce1bb (#2278) 953a4e6 file level param binding (#2275) bea454b implicit decimal param (#2271) 51a35c3 Ram inference...

dependabot[bot]

Yosys SV Support Misrepresented Due to $display

7

Hello, and thank you for assembling this very useful record of SV support in tools! It has been super interesting to follow. ## Problem There are several tests that Yosys...

sifferman

Fix BlackParrot synthesis in Synlig

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This PR applies a filelist patch for BlackParrot core in order to make it synthesizable in Synlig, the patch is the same as the one used in [synlig](https://github.com/chipsalliance/synlig/blob/main/tests/black_parrot/black_parrot_patches/0001_use_synth_filelist.patch). Even though...

robertszczepanski

The https://github.com/pulp-platform/svase project is interesting. It is essentially behaving like a SystemVerilog to Verilog converter using the Slang parser. Since we already include slang, might be cool to include this...

hzeller

The intent of sv-tests is not only to run with the locally compiled runners but as well with the binaries available on the machine and available in the `PATH`. Some...

hzeller

VeeR EL2 core is broken

2

Failing in all tools that do elaboration (slang, verilator) with errors like: ``` ../../../third_party/cores/veer-el2/testbench/uvm/mem/hdl/dccm_monitor.sv:4:28: error: use of undeclared identifier 'uvm_monitor'; did you mean 'dccm_monitor'? class dccm_monitor extends uvm_monitor; ^~~~~~~~~~~ ../../../third_party/cores/veer-el2/testbench/uvm/mem/hdl/dccm_monitor.sv:4:7:...

MikePopoloski

UVM-related tests come with undefined package's import

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About 140 tests from `chapter-16` and `chapter-18` subdirectories start from importing the `uvm_pkg` package before it's definition. The include directive comes right after the import: ``` import uvm_pkg::*; `include "uvm_macros.svh"...

ssmolov

Failing in all tools that do elaboration (slang, verilator) with errors like: ``` ../../../tests/generated/rggen/rggen.sv:156:5: error: interface port 'register_17_bus_if' not connected ) u_block_0 ( ^ ../../../third_party/cores/rggen-sample/block_0.sv:151:23: note: declared here rggen_bus_if.master register_17_bus_if...

MikePopoloski