sv-tests
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chipsalliance
Test suite designed to check compliance with the SystemVerilog standard.
BlackParrot has such example: third_party/cores/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_int_alu.v Either add -sverilog (to treat all files as SystemVerilog) or prefix particular files with -sv option, like: -sv third_party/cores/blackparrot/bp_be/src/v/bp_be_calculator/bp_be_int_alu.v
It would be nice to have some guidelines as to how to contribute properly. I just started a PR and had to update the commits a few times in order...
Hello, is there some way how to specify the correct SystemVerilog version for a specific file? I see that some files are clearly in older standard and because of this...
Maybe I missed a feature but would like to see tracking of expected results. I'd like to encourage use of this project for continuous integration of Verilator, but to do...
I logged the following issue on BlackParrot, but I want to make sure sv-tests does the right thing when creating the project file. On SV-Tests, I have the following error...
See example from https://github.com/google/verible/issues/58 - a `var` is allowed in module port list even though `var` is a keyword in other contexts. ```v module A( input var i, output var...
Sphinx (http://www.sphinx-doc.org/en/master/) is the preferred tool for documenting projects in SymbiFlow. https://readthedocs.org should be used to publish the documentation.
Please consider improving the README with: - How to use RUNNERS= to run just one runner - I figured it out but would be nice to document it. - How...
It would be good to add Verilator in; - [ ] Parse only mode - [ ] simulation mode - [ ] pedantic / strict mode - [ ] other?
Apparently some of the files are like "abstract base classes" so should be marked as parse only. Verilator is failing on these because it parses it and then sees the...
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Test suite designed to check compliance with the SystemVerilog standard.