sv-tests
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Test suite designed to check compliance with the SystemVerilog standard.
* https://cloud.google.com/cloud-build/ * Generous free tier - Say goodbye to managing your own build servers with 120 free build-minutes per day and up to 10 concurrent builds included. Build-minutes are...
Typical SystemVerilog frontend should include: * Preprocessor * Parser * Semantic Analyzer I think that we would need to provide a way to add a new tool covering one or...
There are a bunch of tests that are just numbered, e.g. number_test_6.sv Just looking at these files (or names in the test-outputs), it is not really possible to see what...
Compare SystemVerilog support in Yosys-0.8 verse Yosys-0.9 etc.
Added missing dependencies.
The [README](https://github.com/chipsalliance/sv-tests/blob/master/README.md#running) describes installing some python dependencies ```bash pip3 install --user -r conf/requirements.txt export PATH=~/.local/bin:$PATH ``` Which of course modifiers the users' home directory (and possibly has silent assumptions of...
Bumps [third_party/cores/opentitan](https://github.com/lowRISC/opentitan) from `eec48c4` to `8bf8012`. Commits 8bf8012 [i2c dif] Add headers for functions to control i2c device in the dif 9d0b319 fix(kmac): Check SHA3 done loosely for false value...
Bumps [third_party/tools/moore](https://github.com/fabianschuiki/moore) from `4f91804` to `4423b47`. Commits 4423b47 Update README.md fd59d66 Replace llhd shifts with dynamic extracts and comb shifts (#247) cb0053b Surround moore.mir.concat with conversion casts to pass values...
Bumps [third_party/tests/projf-explore](https://github.com/projf/projf-explore) from `c4d2206` to `7895f5a`. Commits 7895f5a Add sponsor thanks to README. See full diff in compare view Dependabot will resolve any conflicts with this PR as long as...
In order to directly jump to the `CORES` and `IMPORTED` headlines, it would be good if they'd be tagged with an anchor ```HTML ```