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Test suite designed to check compliance with the SystemVerilog standard.

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RedPitaya is a data gathering device using an FPGA. The code is open source and is built with ~30kloc SystemVerilog. So this could make a good example of a real-world...

import-testsuite

slang has an excellent ["Language Support" page @ https://sv-lang.com/language-support.html](https://sv-lang.com/language-support.html). It would be awesome if we generated a similar looking page for each of the tools in sv-tests.

@MikePopoloski has created an awesome ["Language Support" page for slang @ https://sv-lang.com/language-support.html](https://sv-lang.com/language-support.html). It would be good it someone could go through that page and check how it compares to the...

Does it make sense to import the https://github.com/SymbiFlow/XilinxUnisimLibrary library as a third_party test suite?

import-testsuite

[s80x86](https://github.com/jamieiles/80x86) is a 80186 compatible CPU written in SystemVerilog. At some point this can be added as a test case.

tests
import-testsuite

http://fpga.ashishbanerjee.com/opensparc https://github.com/freecores/sparc64soc http://dangerousprototypes.com/blog/2011/01/23/opensparc-on-fpga/

import-testsuite

It would be good to parse the error message and check that it is what is expected.

Some suggestions to make debugging tests easier using the runner: - [ ] When creating logs/.. add a symlink to the .v input files, so a .log is adjacent to...

enhancement
runners

This case looks like syntactically correct Verilog. ```verilog module foo (); always @(posedge 1'd0) begin end endmodule ``` If yes, what would it model? a `never` construct? unreachable state?

enhancement
good first issue
tests

the file external/basejump_stl/bsg_misc/bsg_counter_up_down.variable.v does not exit instead external/basejump_stl/bsg_misc/bsg_counter_up_down_variable.v exists. Yet somehow the command line given to surelog contains the typo ("." instead of "_").