Tag tests with parts of a SystemVerilog frontend required

[mithro]

Typical SystemVerilog frontend should include:

• Preprocessor
• Parser
• Semantic Analyzer

I think that we would need to provide a way to add a new tool covering one or several of these steps. Tests need to contain information about at what stage it could be fed into the chain and at what stage it should pass/fail.

Originally posted by @drom in https://github.com/SymbiFlow/sv-tests/issues/326#issuecomment-542384960

[mithro]

From https://github.com/SymbiFlow/sv-tests/issues/326#issuecomment-542835463

I think that is a good start. I do think there are even a few more levels like;

• Synthesis
• Simulation

[mithro]

@hzeller