Import XilinxUnisimLibrary as a test suite?

[mithro]

Does it make sense to import the https://github.com/SymbiFlow/XilinxUnisimLibrary library as a third_party test suite?

[mithro]

@hzeller @tgorochowik -- Thoughts? Is the UnisimLibrary pure verilog?

[hzeller]

@alainmarcel has it in the Surelog testuite in the meantime ( https://github.com/alainmarcel/Surelog/issues/568 ).

Would be worthwhile to include in sv-tests

[hzeller]

Assigning to Karol for now, please delegate to whoever might be free. Having it in sv-tests will help us see how the tools deal with it (.. and/or how changes in the Unisims files change that)

Here is how they are run in Surelog (they are there in a batchfile, but it is easy to see each individual line is one invocation) https://github.com/alainmarcel/Surelog/blob/master/third_party/tests/XilinxUnisimLibrary/batch.txt

Since we need unique names per test, maybe we just compose it from the filename with some prefix in the generate script. So file RX_BITSLICE.v would become test unisims-RX_BITSLICE maybe.

GitHub

alainmarcel/Surelog

System Verilog 2017 Pre-processor, Parser, UHDM Compiler. Provides IEEE Design/TB VPI and Python AST API. - alainmarcel/Surelog

[mithro]

@alaindargelas - The upstream sim models has been updated with the missing verilog/src/glbl.v file which should make it possible to get further along in the parsing.

[alaindargelas]

Updated, also fixed my grammar for the 2 syntax errors => 0 Syntax errors. All files are parsed 100%.

On Wednesday, July 22, 2020, 10:54:40 AM PDT, Tim Ansell <[email protected]> wrote:  

@alaindargelas - The upstream sim models has been updated with the missing verilog/src/glbl.v file which should make it possible to get further along in the parsing.

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