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Remove implicit width truncation / Don't repeat Verilog's assignment issue in Chisel

49

I just realized that assignment of a larger width signal to a small width signal results in a silent truncation in Chisel. This is one of the worst issues in...

schoeberl

Result of operator ## cannot be assigned to

2

**Type of issue**: bug report | feature request **Impact**: API addition (no impact on existing code) **Development Phase**: proposal **What is the current behavior?** Assume two kinds of Blackbox modules,...

forflo

1. Setup link From the paragraph on https://www.chisel-lang.org > Build Your Own Chisel Projects > See [the setup instructions](https://www.chisel-lang.org/SETUP.md) for how to set up your environment to build Chisel locally....

gonsolo

[GaloisLFSR] Taps defined opposite of Galois Polynomials

3

**Type of issue**: other enhancement **Impact**: no functional change (additional documentation) | API addition (no impact on existing code) **Development Phase**: request **Other information** For a practical example, take the...

michael-etzkorn

hierarchy API not working for inner classes

1

**Type of issue**: bug report **Impact**: API addition (no impact on existing code) I'm considering this an addition b/c it will give the existing API the capability to deal with...

debs-sifive

add chisel level interface to PresetAnnotation

2

### Contributor Checklist - [x] Did you add Scaladoc to every public function/method? - [x] Did you add at least one test demonstrating the PR? - [x] Did you delete...

ekiwi

incrementing a register

1

**Type of issue**: feature request **Impact**: API addition (no impact on existing code) **Development Phase**: proposal Incrementing a register (a counter) is such a common operation. Maybe we should support...

schoeberl

Is there a reason why `Analog()` direction port type is still in [experimental module ](https://www.chisel-lang.org/api/latest/chisel3/experimental/Analog.html)? It has been used for a long time in several project. It's very useful for...

Martoni

Unexpected behaviour of connections for `Reg` defined within `when` context

4

**Type of issue**: bug report **Impact**: unknown **Development Phase**: request **Other information**: see example below **If the current behavior is a bug, please provide the steps to reproduce the problem:**...

johnsbrew

Modifying the name of the module that comes from Chisel Library.

38

**Type of issue**: other enhancement **Impact**: API addition (no impact on existing code) **Development Phase**: proposal **What is the current behavior?** If I create a Module which from Chisel Library,...

starbrilliance