chisel

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Add :<>=, which is a chisel3 API for FIRRTL.<= (to aid in migration from Chisel.:= and Chisel.<>)

5

To migrate code from `Chisel._` to `chisel3._`, the bulk connect operators are very different, which requires a significant rewrite of every bulk connection. However, the old connect operator was actually...

azidar

Updates [org.scalatest:scalatest](https://github.com/scalatest/scalatest) from 3.2.12 to 3.2.13. [GitHub Release Notes](https://github.com/scalatest/scalatest/releases/tag/release-3.2.13) - [Version Diff](https://github.com/scalatest/scalatest/compare/release-3.2.12...release-3.2.13) I'll automatically update this PR to resolve conflicts as long as you don't change it yourself. If you'd...

scala-steward

Enforce port name uniqueness

2

### Contributor Checklist - [x] Did you add Scaladoc to every public function/method? - [x] Did you add at least one test demonstrating the PR? - [x] Did you delete...

adkian-sifive

Updates [org.scalameta:sbt-mdoc](https://github.com/scalameta/mdoc) from 2.3.2 to 2.3.3. [GitHub Release Notes](https://github.com/scalameta/mdoc/releases/tag/v2.3.3) - [Version Diff](https://github.com/scalameta/mdoc/compare/v2.3.2...v2.3.3) I'll automatically update this PR to resolve conflicts as long as you don't change it yourself. If you'd...

scala-steward

Constraint Mux1H to provide deactivated output when given a zero-hot selector.

6

https://github.com/chipsalliance/chisel3/blob/1c5d1b5317a0c9fe7ef9d15138065a817380a1e4/src/main/scala/chisel3/util/Mux.scala#L24 The [documentation](https://www.chisel-lang.org/chisel3/docs/explanations/muxes-and-input-selection.html#mux1h) for Mux1H says "If zero or multiple selectors are set the behavior is undefined", however, the methodology for implementing 1-hot muxes automatically makes the output all zeros...

nicmcd

Unifying Chisel._ and chisel3._ connection semantics

1

**Type of issue**: Feature Request **Is your feature request related to a problem? Please describe.** ## Background: `Chisel._` vs `chisel3._` directionality In `Chisel._`, `IO` has an implicit output direction, and...

mwachs5

**Type of issue**: Feature Request **Is your feature request related to a problem? Please describe.** Questions like [this](https://stackoverflow.com/questions/72908415/calling-dsptools-produces-a-chisel-runtime-error/72941635#72941635) come up fairly regularly on Stack Overflow or Gitter where there is...

jackkoenig

### Contributor Checklist - [x] Did you add Scaladoc to every public function/method? - [ ] Did you add at least one test demonstrating the PR? - [x] Did you...

azidar

Make some usages of suggestName runtime deprecated

4

### Contributor Checklist - [x] Did you add Scaladoc to every public function/method? - [x] Did you add at least one test demonstrating the PR? - [ ] Did you...

mwachs5

ReplSeqMem does not generate memory replacement for cells with specified ReadFirst/WriteFirst

4

Hello, **Type of issue**: bug report **Impact**: API addition (no impact on existing code) **Other information** When SyncReadMem is created with ReadFirst or WriteFirst specified SyncReadMem is not replaced by...

armleo