chisel

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**Description** As part of the LF project onboarding cleanup, our Project Formation Team has recommended implementing a [Developer Certificate of Origin](http://developercertificate.org) (DCO) across the Chisel repositories (and other CHIPS projects)....

bensternthal

BoringUtils: tapAndRead of literal throws error

2

**Type of issue**: Bug Report **Please provide the steps to reproduce the problem:** Use `BoringUtils.tapAndRead` on a literal, example: ``` //> using repository "sonatype-s01:snapshots" //> using scala "2.13.14" //> using...

dtzSiFive

Make Simulator Classes Public for Customization #4240

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This PR makes key simulator classes and objects in chisel3/simulator/package public to enable better customization. It includes: Making SimulatedModule constructor public. Exposing AnySimulatedModule object and methods. Removing sealed modifier from...

kethavath-sanju

value emitVerilog is not a member of circt.stage.ChiselStage

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Hi I got trouble to generate verilog, i got this error: ``` [info] welcome to sbt 1.10.1 (Oracle Corporation Java 23.0.1) [info] loading project definition from /Users/peter/workspace/chisel-examples/hello-world/project [info] loading settings...

quantrpeter

## About this PR 📦 Updates [io.get-coursier:coursier](https://github.com/coursier/coursier) from `2.0.16` to `2.1.24` 📜 [GitHub Release Notes](https://github.com/coursier/coursier/releases/tag/v2.1.24) - [Version Diff](https://github.com/coursier/coursier/compare/v2.0.16...v2.1.24) ## Usage ✅ **Please merge!** I'll automatically update this PR to resolve...

scala-steward

(draft) Change signature of macro-based `chisel3.Bits.unary_~` to fix IntelliJ highlighting issue

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Hello, I am from the IntelliJ Scala Plugin team We have an error report about `~` method not being resolved in IntelliJ with Scala Plugin: https://youtrack.jetbrains.com/issue/SCL-15350/Operators-not-recognized-chisel3-library The method is macro-based....

unkarjedy

### Contributor Checklist - [x] Did you add Scaladoc to every public function/method? - [x] Did you add at least one test demonstrating the PR? - [x] Did you delete...

tmckay-sifive

Initialize (FPGA) memory in Chisel 6

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**Type of issue**: Bug Report **Please provide the steps to reproduce the problem:** Initializing memory is broken now. See for an error: https://github.com/schoeberl/chisel-book/actions/runs/11708082480/job/32608967721 The code is here: https://github.com/schoeberl/chisel-book/blob/6ee398bd61bf8cdee02abcd780a2035b8cff4d1a/src/main/scala/memory.scala#L107-L130 and the...

schoeberl

Regarding the loss of active reset behavior of Reg or being overridden by RegInit.

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**Type of issue**: Bug Report **Please provide the steps to reproduce the problem:** Using the latest chisel-template (corresponding to chisel v6.0.0), emit the following code as System Verilog, and compare...

linmoIO

[choice] Adds a means to declare a choice group without use

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Per @seldridge's suggestion here I add analog of `addLayer` for `ModuleChoice` called `addGroup`. This permits defining a group in a circuit without necessarily using that group in a circuit, allowing...

davidbiancolin